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rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a lc 2 mos 4-channel, 12-bit simultaneous sampling data acquisition system ad7874 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 functional block diagram agnd clk dgnd db11 db0 v ss cs 12-bit dac v in1 v in2 v in3 v in4 comp reference buffer int rd ad7874 convst v dd v dd ref in ref out 3v reference data registers sar mux control logic internal clock track/ hold 3 track/ hold 4 track/ hold 2 track/ hold 1 general description the ad7874 is a four-channel simultaneous sampling, 12-bit data acquisition system. the part contains a high speed 12-bit adc, on-chip reference, on-chip clock and four track/hold am- plifiers. this latter feature allows the four input channels to be sampled simultaneously, thus preserving the relative phase information of the four input channels, which is not possible if all four channels share a single track/hold amplifier. this makes the ad7874 ideal for applications such as phased-array sonar and ac motor controllers where the relative phase information is important. the aperture delay of the four track/hold amplifiers is small and specified with minimum and maximum limits. this allows sev- eral ad7874s to sample multiple input channels simultaneously without incurring phase errors between signals connected to several devices. a reference output/reference input facility also allows several ad7874s to be driven from the same reference source. in addition to the traditional dc accuracy specifications such as linearity, full-scale and offset errors, the ad7874 is also fully specified for dynamic performance parameters including distor- tion and signal-to-noise ratio. the ad7874 is fabricated in analog devices linear compat- ible cmos (lc 2 mos) process, a mixed technology process that combines precision bipolar circuits with low-power cmos logic. the part is available in a 28-pin, 0.6" wide, plastic or her- metic dual-in-line package (dip), in a 28-terminal leadless ce- ramic chip carrier (lccc) and in a 28-pin soic. features four on-chip track/hold amplifiers simultaneous sampling of 4 channels fast 12-bit adc with 8 m s conversion time/channel 29 khz sample rate for all four channels on-chip reference 6 10 v input range 6 5 v supplies applications sonar motor controllers adaptive filters digital signal processing product highlights 1. simultaneous sampling of four input channels. four input channels, each with its own track/hold amplifier, allow simultaneous sampling of input signals. track/hold ac- quisition time is 2 m s, and the conversion time per channel is 8 m s, allowing 29 khz sample rate for all four channels. 2. tight aperture delay matching. the aperture delay for each channel is small and the aperture delay matching between the four channels is less than 4 ns. additionally, the aperture delay specification has upper and lower limits allowing multiple ad7874s to sample more than four channels. 3. fast microprocessor interface. the high speed digital interface of the ad7874 allows direct connection to all modern 16-bit microprocessors and digital signal processors.
rev. c C2C ad7874Cspecifications (v dd = +5 v, v ss = C5 v, agnd = dgnd = 0 v, ref in = +3 v, f clk = 2.5 mhz external. all specifications t min to t max unless otherwise noted.) parameter a version b version s version units test conditions/comments sample-and-hold acquisition time 2 to 0.01% 2 2 2 m s max droop rate 2, 3 1 1 2 mv/ms max C3 db small signal bandwidth 3 500 500 500 khz typ v in = 500 mv p-p aperture delay 2 0 0 0 ns min 40 40 40 ns max aperture jitter 2, 3 200 200 200 ps typ aperture delay matching 2 4 4 4 ns max sample-and-hold and adc dynamic performance signal-to-noise ratio 70 71 70 db min f in = 10 khz sine wave, f sample = 29 khz total harmonic distortion C78 C80 C78 db max f in = 10 khz sine wave, f sample = 29 khz peak harmonic or spurious noise C78 C80 C78 db max f in = 10 khz sine wave, f sample = 29 khz intermodulation distortion fa = 9 khz, fb = 9.5 khz, f sample = 29 khz 2nd order terms C80 C80 C80 db max 3rd order terms C80 C80 C80 db max channel-to-channel isolation 2 C80 C80 C80 db max dc accuracy resolution 12 12 12 bits relative accuracy 1 1/2 1 lsb max differential nonlinearity 1 1 1 lsb max no missing codes guaranteed positive full-scale error 4 5 5 5 lsb max any channel negative full-scale error 4 5 5 5 lsb max any channel full-scale error match 5 5 5 lsb max between channels bipolar zero error 5 5 5 lsb max any channel bipolar zero error match 4 4 4 lsb max between channels analog inputs input voltage range 10 10 10 volts input current 600 600 600 m a max reference outputs ref out 333v nom ref out error @ +25 c 0.33 0.33 0.33 % max t min to t max 1 1 1 % max ref out temperature coefficient 35 35 35 ppm/ c typ reference load change 1 1 2 mv max reference load current change (0C500 m a) reference load should not be changed during conversion reference input input voltage range 2.85/3.15 2.85/3.15 2.85/3.15 v min/v max 3 v 5% input current 1 1 1 m a max input capacitance 3 10 10 10 pf max logic inputs input high voltage, v inh 2.4 2.4 2.4 v min v dd = 5 v 5% input low voltage, v inl 0.8 0.8 0.8 v max v dd = 5 v 5% input current, i in 10 10 10 m a max v in = 0 v to v dd input capacitance, c in 3 10 10 10 pf max logic outputs output high voltage, v oh 4.0 4.0 4.0 v min v dd = 5 v 5%; i source = 40 m a output low voltage, v ol 0.4 0.4 0.4 v max v dd = 5 v 5%; i sink = 1C6 ma db0Cdb11 floating-state leakage current 10 10 10 m a max v in = 0 v to v dd floating-state output capacitance 10 10 10 pf max output coding 2s complement power requirements v dd +5 +5 +5 v nom 5% for specified performance v ss C5 C5 C5 v nom 5% for specified performance i dd 18 18 18 ma max cs = rd = convst = +5 v; typically 12 ma i ss 12 12 12 ma max cs = rd = convst = +5 v; typically 8 ma power dissipation 150 150 150 mw max cs = rd = convst = +5 v; typically 100 mw notes 1 temperature ranges are as follows: a, b versions: C40 c to +85 c; s version: C55 c to +125 c. 2 see terminology. 3 sample tested @ +25 c to ensure compliance. 4 measured with respect to the ref in voltage and includes bipolar offset error. 5 for capacitive loads greater than 50 pf a series resistor is required. specifications subject to change without notice.
ad7874 rev. c C3C timing characteristics 1 parameter a, b versions s version units conditions/comments t 1 50 50 ns min convst pulse width t 2 0 0 ns min cs to rd setup time t 3 60 70 ns min rd pulse width t 4 0 0 ns min cs to rd hold time t 5 60 60 ns max rd to int delay t 6 2 57 70 ns max data access time after rd t 7 3 55 ns min bus relinquish time after rd 45 50 ns max t 8 130 150 ns min delay time between reads t conv 31 31 m s min convst to int , external clock 32.5 32.5 m s max convst to int , external clock 31 31 m s min convst to int , internal clock 35 35 m s max convst to int , internal clock t clk 10 10 m s max minimum input clock period notes 1 timing specifications in bold print are 100% production tested. all other times are sample tested at +25 c to ensure compliance. all input signals are specified with tr = tf = 5 ns (10% to 90% of +5 v) and timed from a voltage level of 1.6 v. 2 t 6 is measured with the load circuit of figure 1 and defined as the time required for an output to cross 0.8 v or 2.4 v. 3 t 7 is derived from the measured time taken by the data outputs to change 0.5 v when loaded with the circuit of figure 2. the measured number is then extrapolated back to remove the effects of charging or discharging the 50 pf capacitor. this means that the time, t 7 , quoted in the timing characteristics is the true bus relinquish time of the part and as such is independent of external bus loading capacitances. specifications subject to change without notice. (v dd = +5 v 6 5%, v ss = C5 v 6 5%, agnd = dgnd = o v, t clk = 2.5 mhz external unless otherwise noted.) absolute maximum ratings* (t a = +25 c unless otherwise noted) v dd to agnd . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +7 v v dd to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +7 v v ss to agnd . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 v to C7 v agnd to dgnd . . . . . . . . . . . . . . . . C0.3 v to v dd + 0.3 v v in to agnd . . . . . . . . . . . . . . . . . . . . . . . . . C15 v to +15 v ref out to agnd . . . . . . . . . . . . . . . . . . . . . . . 0 v to v dd digital inputs to dgnd . . . . . . . . . . . C0.3 v to v dd + 0.3 v digital outputs to dgnd . . . . . . . . . . C0.3 v to v dd + 0.3 v operating temperature range commercial (a, b versions) . . . . . . . . . . . C40 c to +85 c extended (s version) . . . . . . . . . . . . . . . . C55 c to +125 c storage temperature range . . . . . . . . . . . . C65 c to +150 c lead temperature (soldering, 10 secs) . . . . . . . . . . . +300 c power dissipation (any package) to +75 c . . . . . . 1,000 mw derates above +75 c by . . . . . . . . . . . . . . . . . . . . 10 mw/ c *stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. to output pin 1.6ma 2.1v + 200 m a 50pf figure 1. load circuit for access time to output pin 1.6ma 2.1v + 200 m a 50pf figure 2. load circuit for bus relinquish time warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad7874 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad7874 rev. c C4C terminology acquisition time acquisition time is the time required for the output of the track/hold amplifiers to reach their final values, within 1/2 lsb, after the falling edge of int (the point at which the track/ holds return to track mode). this includes switch delay time, slewing time and settling time for a full-scale voltage change. aperture delay aperture delay is defined as the time required by the internal switches to disconnect the hold capacitors from the inputs. this produces an effective delay in sample timing. it is measured by applying a step input and adjusting the convst input position until the output code follows the step input change. aperture delay matching aperture delay matching is the maximum deviation in aperture delays across the four on-chip track/hold amplifiers. aperture jitter aperture jitter is the uncertainty in aperture delay caused by internal noise and variation of switching thresholds with signal level. droop rate droop rate is the change in the held analog voltage resulting from leakage currents. channel-to-channel isolation channel-to-channel isolation is a measure of the level of crosstalk between channels. it is measured by applying a full- scale 1 khz signal to the other three inputs. the figure given is the worst case across all four channels. snr, thd, imd see dynamic specifications section. pin configurations dip and soic v in1 v in2 v in4 v in3 ref in agnd db0 (lsb) v dd v ss ref out clk db1 v dd db2 db11 (msb) db3 db10 db4 db9 db5 db8 db6 dgnd db7 13 18 1 2 28 27 5 6 7 24 23 22 3 4 26 25 821 920 10 19 11 11 12 17 16 14 15 top view (not to scale) ad7874 int convst rd cs lccc v dd clk v dd v in4 v in2 v in1 db9 db8 db6 dgnd db7 ref out ref in db1 agnd db0 (lsb) db10 db11 (msb) db4 db5 v ss v in3 db3 db2 ad7874 27 1 28 226 3 4 25 22 24 23 21 19 20 18 17 12 13 16 14 15 11 10 9 8 7 6 5 top view (not to scale) convst rd cs int
ad7874 rev. c C5C pin function description pin mnemonic description 1v in1 analog input channel 1. this is the first of the four input channels to be converted in a con- version cycle. analog input voltage range is 10 v. 2v in2 analog input channel 2. analog input voltage range is 10 v. 3v dd positive supply voltage, +5 v 5%. this pin should be decoupled to agnd. 4 int interrupt. active low logic output indicating converter status. see figure 7. 5 convst convert start. logic input. a low to high transition on this input puts the track/hold into its hold mode and starts conversion. the four channels are converted sequentially, channel 1 to channel 4. the convst input is asynchronous to clk and independent of cs and rd . 6 rd read. active low logic input. this input is used in conjunction with cs low to enable the data outputs. four successive reads after a conversion will read the data from the four chan- nels in the sequence, channel 1, 2, 3, 4. 7 cs chip select. active low logic input. the device is selected when this input is active. 8 clk clock input. an external ttl-compatible clock may be applied to this input pin. alterna- tively, tying this pin to v ss enables the internal laser trimmed clock oscillator. 9v dd positive supply voltage, +5 v 5%. same as pin 3; both pins must be tied together at the package. this pin should be decoupled to dgnd. 10 db11 data bit 11 (msb). three-state ttl output. output coding is 2s complement. 11C13 db10Cdb8 data bit 10 to data bit 8. three-state ttl outputs. 14 dgnd digital ground. ground reference for digital circuitry. 15C21 db7Cdb1 data bit 7 to data bit 1. three-state ttl outputs. 22 db0 data bit 0 (lsb). three-state ttl output. 23 agnd analog ground. ground reference for track/hold, reference and dac. 24 ref in voltage reference input. the reference voltage for the part is applied to this pin. it is inter- nally buffered, requiring an input current of only 1 m a. the nominal reference voltage for correct operation of the ad7874 is 3 v. 25 ref out voltage reference output. the internal 3 v analog reference is provided at this pin. to oper- ate the ad7874 with internal reference, ref out is connected to ref in. the external load capability of the reference is 500 m a. 26 v ss negative supply voltage, C5 v 5%. 27 v in3 analog input channel 3. analog input voltage range is 10 v. 28 v in4 analog input channel 4. analog input voltage range is 10 v. ordering guide relative temperature snr accuracy package model 1 range (dbs) (lsb) option 2 ad7874an C40 c to +85 c 70 min 1 max n-28 ad7874bn C40 c to +85 c 72 min 1/2 max n-28 ad7874ar C40 c to +85 c 70 min 1 max r-28 ad7874br C40 c to +85 c 72 min 1/2 max r-28 ad7874aq C40 c to +85 c 70 min 1 max q-28 AD7874BQ C40 c to +85 c 72 min 1/2 max q-28 ad7874sq 3 C55 c to +125 c 70 min 1 max q-28 ad7874se 3 C55 c to +125 c 70 min 1 max e-28a notes 1 to order mil-std-883, class b processed parts, add /883b to part number. contact 1 our local sales office for military data sheet and availability. 2 e = leaded ceramic chip carrier; n = plastic dip; q = cerdip; r = soic. 3 available to /883b processing only.
ad7874 rev. c C6C converter details the ad7874 is a complete 12-bit, 4-channel data acquisition system. it is comprised of a 12-bit successive approximation adc, four high speed track/hold circuits, a four-channel analog multiplexer and a 3 v zener reference. the adc uses a succes- sive approximation technique and is based on a fast-settling, voltage switching dac, a high speed comparator, a fast cmos sar and high speed logic. conversion is initiated on the rising edge of convst . all four input track/holds go from track to hold on this edge. conversion is first performed on the channel 1 input voltage, then channel 2 is converted and so on. the four results are stored in on-chip registers. when all four conversions have been completed, int goes low indicating that data can be read from these locations. the conversion sequence takes either 78 or 79 rising clock edges depending on the synchronization of convst with clk. in- ternal delays and reset times bring the total conversion time from convst going high to int going low to 32.5 m s maxi- mum for a 2.5 mhz external clock. the ad7874 uses an im- plicit addressing scheme whereby four successive reads to the same memory location access the four data words sequentially. the first read accesses channel 1 data, the second read accesses channel 2 data and so on. individual data registers cannot be accessed independently. internal reference the ad7874 has an on-chip temperature compensated buried zener reference which is factory trimmed to 3 v 10 mv (see figure 3). the reference voltage is provided at the ref out pin. this reference can be used to provide both the reference voltage for the adc and the bipolar bias circuitry. this is achieved by connecting ref out to ref in. temperature compensation ad7874 v dd v ss ref out figure 3. ad7874 internal reference the reference can also be used as a reference for other compo- nents and is capable of providing up to 500 m a to an external load. in systems using several ad7874s, using the ref out of one device to provide the ref in for the other devices ensures good full-scale tracking between all the ad7874s. because the ad7874 ref in is buffered, each ad7874 presents a high im- pedance to the reference so one ad7874 ref out can drive several ad7874 ref ins. the maximum recommended capacitance on ref out for normal operation is 50 pf. if the reference is required for other system uses, it should be decoupled to agnd with a 200 w re- sistor in series with a parallel combination of a 10 m f tantalum capacitor and a 0.1 m f ceramic capacitor. external reference in some applications, the user may require a system reference or some other external reference to drive the ad7874 reference in- put. figure 4 shows how the ad586 5 v reference can be used to provide the 3 v reference required by the ad7874 ref in. gnd +v in v out agnd 10k w 15k w 1k w v in1 to internal comparator track/hold 1 to adc reference circuitry 7r* 2.1r* 3r* ad7874** ref in 15v + ad586 *r = 3.6k w typ **additional pins omitted for clarity figure 4. ad586 driving ad7874 ref in track-and-hold amplifier the track-and-hold amplifier on each analog input of the ad7874 allows the adc to accurately convert an input sine wave of 20 v p-p amplitude to 12-bit accuracy. the input band- width of the track/hold amplifier is greater than the nyquist rate of the adc even when the adc is operated at its maximum throughput rate. the small signal 3 db cutoff frequency occurs typically at 500 khz. the four track/hold amplifiers sample their respective input channels simultaneously. the aperture delay of the track/hold circuits is small and, more importantly, is well matched across the four track/holds on one device and also well matched from device to device. this allows the relative phase information be- tween different input channels to be accurately preserved. it also allows multiple ad7874s to sample more than four channels simultaneously. the operation of the track/hold amplifiers is essentially transpar- ent to the user. once conversion is initiated, the four channels are automatically converted and there is no need to select which channel is to be digitized. analog input the analog input of channel 1 of the ad7874 is as shown in figure 4. the analog input range is 10 v into an input resis- tance of typically 30 k w . the designed code transitions occur midway between successive integer lsb values (i.e., 1/2 lsb, 3/2 lsbs, 5/2 lsbs, . . . fs C 3/2 lsbs). the output code is 2s complement binary with 1 lsb = fs/4096 = 20 v/4096 = 4.88 mv. the ideal input/output transfer function is shown in figure 5.
ad7874 rev. c C7C fs 2 fs=20v 1lsb = 4096 fs output code 0v input voltage 011...111 011...110 000...010 000...001 000...000 111...111 111...110 100...001 100...000 fs + 2 1lsb figure 5. input/output transfer function offset and full-scale adjustment in most digital signal processing (dsp) applications, offset and full-scale errors have little or no effect on system performance. offset error can always be eliminated in the analog domain by ac coupling. full-scale error effect is linear and does not cause problems as long as the input signal is within the full dynamic range of the adc. invariably, some applications will require that the input signal span the full analog input dynamic range. in such applications, offset and full-scale error will have to be adjusted to zero. figure 6 shows a circuit which can be used to adjust the offset and full-scale errors on the ad7874 (channel 1 is shown for ex- ample purposes only). where adjustment is required, offset er- ror must be adjusted before full-scale error. this is achieved by trimming the offset of the op amp driving the analog input of the ad7874 while the input voltage is a 1/2 lsb below analog ground. the trim procedure is as follows: apply a voltage of C2.44 mv (C1/2 lsb) at v 1 in figure 6 and adjust the op amp offset voltage until the adc output code flickers between 1111 1111 1111 and 0000 0000 0000. v 1 r1 10k w r2 500 w r3 10k w v in1 agnd ad7874* *additional pins omitted for clarity input range = 10v 10k w r5 10k w r4 figure 6. ad7874 full-scale adjust circuit gain error can be adjusted at either the first code transition (adc negative full scale) or the last code transition (adc posi- tive full scale). the trim procedures for both cases are as follows: positive full-scale adjust apply a voltage of +9.9927 v (fs/2 C 3/2 lsbs) at v 1 . adjust r2 until the adc output code flickers between 0111 1111 1110 and 0111 1111 1111. negative full-scale adjust apply a voltage of C9.9976 v ( Cfs + 1/2 lsb) at v 1 and adjust r2 until the adc output code flickers between 1000 0000 0000 and 1000 0000 0001. an alternative scheme for adjusting full-scale error in systems which use an external reference is to adjust the voltage at the ref in pin until the full-scale error for any of the channels is adjusted out. the good full-scale matching of the channels will ensure small full-scale errors on the other channels. timing and control conversion is initiated on the ad7874 by asserting the convst input. this convst input is an asynchronous input which is independent of the adc clock. this is essential for applications where precise sampling in time is important. in these applications, the signal sampling must occur at exactly equal intervals to minimize errors due to sampling uncertainty or jitter. in these cases, the convst input is driven from a timer or precise clock source. once conversion is started, convst should not be asserted again until conversion is com- plete on all four channels. in applications where precise time interval sampling is not criti- cal, the convst pulse can be generated from a microproces- sor write or read line gated with a decoded address (different to the ad7874 cs address). convst should not be derived from a decoded address alone because very short convst pulses (which may occur in some microprocessor sys- tems as the address bus is changing at the start of an instruction cycle) could initiate a conversion. all four track/hold amplifiers go from track to hold on the rising edge of the convst pulse. the four track/hold amplifiers re- main in their hold mode while all four channels are converted. the rising edge of convst also initiates a conversion on the channel 1 input voltage (v in1 ). when conversion is complete on channel 1, its result is stored in data register 1, one of four on-chip registers used to store the conversion results. when the result from the first conversion is stored, conversion is initiated on the voltage held by track/hold 2. when conversion has been completed on the voltage held by track/hold 4 and its result is stored in data register 4, int goes low to indicate that the conversion process is complete. the sequence in which the channel conversions takes place is automatically taken care of by the ad7874. this means that the user does not have to provide address lines to the ad7874 or worry about selecting which channel is to be digitized. reading data from the device consists of four read operations to the same microprocessor address. addressing of the four on-chip data registers is again automatically taken care of by the ad7874.
ad7874 rev. c C8C the first read operation to the ad7874 after conversion always accesses data from data register 1 (i.e., the conversion result from the v in1 input). int is reset high on the falling edge of rd during this first read operation. the second read always ac- cesses data from data register 2 and so on. the address pointer is reset to point to data register 1 on the rising edge of convst . a read operation to the ad7874 should not be at- tempted during conversion. the timing diagram for the ad7874 conversion sequence is shown in figure 7. ch1 data ch2 data ch3 data ch4 data data int cs rd convst high-impedance track/holds go into hold high- z high-z t 1 t conv t acquisition t 5 t 2 t 8 t 4 t 3 t 7 t 6 high- z high- z times t 2 , t 3 , t 4 , t 6 , t 7 , and t 8 are the same for all four read operations. figure 7. ad7874 timing diagram ad7874 dynamic specifications the ad7874 is specified and 100% tested for dynamic perfor- mance specifications as well as traditional dc specifications such as integral and differential nonlinearity. these ac specifications are required for the signal processing applications such as phased array sonar, adaptive filters and spectrum analysis. these applications require information on the adcs effect on the spectral content of the input signal. hence, the parameters for which the ad7874 is specified include snr, harmonic dis- tortion, intermodulation distortion and peak harmonics. these terms are discussed in more detail in the following sections. signal-to-noise ratio (snr) snr is the measured signal to noise ratio at the output of the adc. the signal is the rms magnitude of the fundamental. noise is the rms sum of all the nonfundamental signals up to half the sampling frequency (fs/2) excluding dc. snr is depen- dent upon the number of quantization levels used in the digiti- zation process; the more levels, the smaller the quantization noise. the theoretical signal to noise ratio for a sine wave input is given by snr = ( 6.02 n + 1.76 ) db (1) where n is the number of bits. thus for an ideal 12-bit converter, snr = 74 db. the output spectrum from the adc is evaluated by applying a sine wave signal of very low distortion to the v in input which is sampled at a 29 khz sampling rate. a fast fourier transform (fft) plot is generated from which the snr data can be ob- tained. figure 8 shows a typical 2048 point fft plot of the ad7874bn with an input signal of 10 khz and a sampling frequency of 29 khz. the snr obtained from this graph is 73.2 db. it should be noted that the harmonics are taken into account when calculating the snr. figure 8. ad7874 fft plot effective number of bits the formula given in equation 1 relates the snr to the number of bits. rewriting the formula, as in equation 2, it is possible to get a measure of performance expressed in effective number of bits (n). n = snr - 1. 7 6 6.02 (2) the effective number of bits for a device can be calculated di- rectly from its measured snr. figure 9 shows a typical plot of effective number of bits versus frequency for an ad7874bn with a sampling frequency of 29 khz. the effective number of bits typically falls between 11.75 and 11.87 corresponding to snr figures of 72.5 db and 73.2 db. z figure 9. effective numbers of bits vs. frequency
ad7874 rev. c C9C total harmonic distortion (thd) total harmonic distortion (thd) is the ratio of the rms sum of harmonics to the rms value of the fundamental. for the ad7874, thd is defined as thd = 20 log v 2 2 + v 3 2 + v 4 2 + v 5 2 + v 6 2 v 1 where v 1 is the rms amplitude of the fundamental and v 2 , v 3 , v 4 , v 5 and v 6 are the rms amplitudes of the second through the sixth harmonic. the thd is also derived from the fft plot of the adc output spectrum. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3 . . ., etc. intermodulation terms are those for which neither m or n are equal to zero. for example, the second order terms include (fa + fb) and (fa C fb) while the third order terms include (2fa + fb), (2fa C fb), (fa + 2fb) and (fa C 2fb). using the ccif standard where two input frequencies near the top end of the input bandwidth are used, the second and third order terms are of different significance. the second order terms are usually distanced in frequency from the original sine waves while the third order terms are usually at a frequency close to the input frequencies. as a result, the second and third order terms are specified separately. the calculation of the intermodu- lation distortion is as per the thd specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the fundamental ex pressed in dbs. in t his case, the input consists of two, equal amplitude, low distortion sine waves. figure 10 shows a typical imd plot for the ad7874. figure 10. ad7874 imd plot peak harmonic or spurious noise harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the adc output spec- trum (up to fs/2 and excluding dc) to the rms value of the fun- damental. normally, the value of this specification will be determined by the largest harmonic in the spectrum, but for parts where the harmonics are buried in the noise floor the peak will be a noise peak. ac linearity plot when a sine wave of specified frequency is applied to the v in in- put of the ad7874 and several million samples are taken, a his- togram showing the frequency of occurrence of each of the 4096 adc codes can be generated. from this histogram data it is possible to generate an ac integral linearity plot as shown in fig- ure 11. this shows very good integral linearity performance from the ad7874 at an input frequency of 10 khz. the absence of large spikes in the plot shows good differential linearity. sim- plified versions of the formulae used are outlined below. inl ( i ) = ( v ( i ) - v ( o )) 4096 v ( fs ) - v ( o ) ? ? - i where inl ( i ) is the integral linearity at code i. v ( fs ) and v ( o ) are the estimated full-scale and offset transitions, and v ( i ) is the es- timated transition for the i th code. v ( i ), the estimated code transition point is derived as follows: v ( i ) =- a cos p cum ( i ) [] n where a is the peak signal amplitude, n is the number of histo- gram samples and cum ( i ) = n = o i ? v ( n ) occurrences figure 11. ad7874 ac inl plot
ad7874 rev. c C10C microprocessor interfacing the ad7874 high speed bus timing allows direct interfacing to dsp processors as well as modern 16-bit microprocessors. suitable microprocessor interfaces are shown in figures 12 through 16. ad7874Cadsp-2100 interface figure 12 shows an interface between the ad7874 and the adsp-2100. conversion is initiated using a timer which allows very accurate control of the sampling instant on all four chan- nels. the ad7874 int line provides an interrupt to the adsp- 2100 when conversion is completed on all four channels. the four conversion results can then be read from the ad7874 using four successive reads to the same memory address. the follow- ing instruction reads one of the four results (this instruction is repeated four times to read all four results in sequence): mr0 = dm(adc) where mr0 is the adsp-2100 mr0 register and adc is the ad7874 address. timer dma0 dma13 dmd15 dmd0 dms en addr decode address bus adsp-2100 (adsp-2101/ adsp-2102) * additional pins omitted for clarity data bus convst cs db11 db0 rd int ad7874* irqn dmrd (rd) figure 12. ad7874Cadsp-2100 interface ad7874Cadsp-2101/adsp-2102 interface the interface outlined in figure 12 also forms the basis for an interface between the ad7874 and the adsp-2101/adsp-2102. the read line of the adsp-2101/adsp-2102 is labeled rd . in this interface, the rd pulse width of the processor can be programmed using the data memory wait state control regis- ter. the instruction used to read one of the four results is as outlined for the adsp-2100. ad7874Ctms32010 interface an interface between the ad7874 and the tms32010 is shown in figure 13. once again the conversion is initiated using an ex- ternal timer and the tms32010 is interrupted when all four conversions have been completed. the following instruction is used to read the conversion results from the ad7874: in d,adc where d is data memory address and adc is the ad7874 address. pa0 pa2 d15 d0 men en addr decode address bus timer data bus convst cs db11 db0 rd int ad7874* tms32010 *additional pins omitted for clarity int den figure 13. ad7874Ctms32010 interface ad7874Ctms320c25 interface figure 14 shows an interface between the ad7874 and the tms320c25. as with the two previous interfaces, conversion is initiated with a timer and the processor is interrupted when the conversion sequence is completed. the tms320c25 does not have a separate rd output to drive the ad7874 rd input di- rectly. this has to be generated from the processor strb and r/ w outputs with the addition of some logic gates. the rd sig- nal is or-gated with the msc signal to provide the one wait state required in the read cycle for correct interface timing. conversion results are read from the ad7874 using the follow- ing instruction: in d,adc where d is data memory address and adc is the ad7874 address. a0 a15 d15 d0 is en addr decode address bus timer data bus convst cs db11 db0 rd int ad7874* tms320c25 *additional pins omitted for clarity intn r/w strb msc ready figure 14. ad7874Ctms320c25 interface
ad7874 rev. c C11C some applications may require that the conversion is initiated by the microprocessor rather than an external timer. one option is to decode the ad7874 convst from the address bus so that a write operation starts a conversion. data is read at the end of the conversion sequence as before. figure 16 shows an example of initiating conversion using this method. note that for all interfaces, a read operation should not be attempted dur- ing conversion. ad7874Cmc68000 interface an interface between the ad7874 and the mc68000 is shown in figure 15. as before, conversion is initiated using an external timer. the ad7874 int line can be used to interrupt the pro- cessor or, alternatively, software delays can ensure that conver- sion has been completed before a read to the ad7874 is attempted. because of the nature of its interrupts, the 68000 requires additional logic (not shown in figure 15) to allow it to be interrupted correctly. for further information on 68000 in- terrupts, consult the 68000 users manual. the mc68000 as and r/ w outputs are used to generate a separate rd input signal for the ad7874. cs is used to drive the 68000 dtack input to allow the processor to execute a normal read operation to the ad7874. the conversion results are read using the following 68000 instruction: move.w adc,d0 where d0 is the 68000 d0 register and adc is the ad7874 address. a0 a15 d15 d0 addr decode address bus data bus convst cs db11 db0 rd ad7874* mc68000 *additional pins omitted for clarity r/w as en dtack timer figure 15. ad7874Cmc68000 interface ad7874C8086 interface figure 16 shows an interface between the ad7874 and the 8086 microprocessor. unlike the previous interface examples, the microprocessor initiates conversion. this is achieved by gating the 8086 wr signal with a decoded address output (different to the ad7874 cs address). the ad7874 int line is used to in- terrupt the microprocessor when the conversion sequence is completed. data is read from the ad7874 using the following instruction: mov ax,adc where ax is the 8086 accumulator and adc is the ad7874 address. ale ad15 ad0 addr decode address bus address/data bus convst cs db11 db0 rd ad7874* 8086 *additional pins omitted for clarity wr rd latch figure 16. ad7874C8086 interface
ad7874 rev. c C12C applications vector motor control the current drawn by a motor can be split into two compo- nents: one produces torque and the other produces magnetic flux. for optimal performance of the motor, these two compo- nents should be controlled independently. in conventional methods of controlling a three-phase motor, the current (or voltage) supplied to the motor and the frequency of the drive are the basic control variables. however, both the torque and flux are functions of current (or voltage) and frequency. this cou- pling effect can reduce the performance of the motor because, for example, if the torque is increased by increasing the fre- quency, the flux tends to decrease. vector control of an ac motor involves controlling phase in addi- tion to drive and current frequency. controlling the phase of the motor requires feedback information on the position of the rotor relative to the rotating magnetic field in the motor. using this information, a vector controller mathematically transforms the three phase drive currents into separate torque and flux compo- nents. the ad7874, with its four-channel simultaneous sam- pling capability, is ideally suited for use in vector motor control applications. a block diagram of a vector motor control application using the ad7874 is shown in figure 17. the position of the field is de- rived by determining the current in each phase of the motor. only two phase currents need to be measured because the third can be calculated if two phases are known. channel 1 and channel 2 of the ad7874 are used to digitize this information. simultaneous sampling is critical to maintain the relative phase information between the two channels. a current sensing isola- tion amplifier, transformer or hall effect sensor is used between the motor and the ad7874. rotor information is obtained by measuring the voltage from two of the inputs to the motor. channel 3 and channel 4 of the ad7874 are used to obtain this information. once again the relative phase of the two channels is important. a dsp microprocessor is used to perform the mathematical transformations and control loop calculations on the information fed back by the ad7874. voltage attenuators dac dac dac torque setpoint in1 v v in4 v in3 v in2 *additional pins omitted for clarity torque & flux control loop calculations & two to three phase information transformation to torque & flux current components flux setpoint drive circuitry isolation amplifiers ad7874* dsp microprocessor i c i b i a v b v a 3 phase motor figure 17. vector motor control using the ad7874
ad7874 rev. c C13C multiple ad7874s figure 18 shows a system where a number of ad7874s can be configured to handle multiple input channels. this type of con- figuration is common in applications such as sonar, radar, etc. the ad7874 is specified with maximum and minimum limits on aperture delay. this means that the user knows the maximum difference in the sampling instant between all channels. this al- lows the user to maintain relative phase information between the different channels. a common read signal from the microprocessor drives the rd input of all ad7874s. each ad7874 is designated a unique ad- dress selected by the address decoder. the reference output of ad7874 number 1 is used to drive the reference input of all other ad7874s in the circuit shown in figure 18. one ref out pin can drive several ad7874 ref in pins. alternatively, an external or system reference can be used to drive all ref in inputs. a common reference ensures good full-scale tracking be- tween all channels. ad7874(1) ad7874(2) ad7874(n) cs rd cs rd cs rd rd address ref out ref in ref in address decode v ch5 v ch6 v ch7 v ch8 v ch1 v ch2 v ch3 v ch4 v chm v chm+1 v chm+2 v chm+3 figure 18. multiple ad7874s in multichannel system data acquisition board figure 20 shows the ad7874 in a data acquisition circuit. the corresponding printed circuit board (pcb) layout and silkscreen are shown in figures 21 to 23. a 26-contact idc connector pro- vides for a microprocessor connection to the board. a component grid is provided near the analog inputs on the pcb which may be used to provide antialiasing filters for the analog input channels or to provide signal conditioning circuitry. to facilitate this option, four shorting plugs (labeled lk1 to lk4 on the pcb) are provided on the analog inputs, one plug per input. if the shorting plug for a particular channel is used, the input signal connects to the buffer amplifier driving the ana- log input of the adc. if the shorting plug is omitted, a wire link can be used to connect the input signal to the pcb component grid. microprocessor connections to the board are made via a 26- contact idc connector, skt8, the pinout for which is shown in figure 19. this connector contains all data, control and status signals of the ad7874 (with the exception of the clk input and the convst input which are provided via skt5 and skt7, respectively). it also contains decoded r/ w and strb inputs which are necessary for tms32020 interfacing (and also for 68000 interfacing although pin labels on the 68000 are dif- ferent). note that the ad7874 cs input must be decoded prior to the ad7874 evaluation board. skt1, skt2, skt3 and skt4 provide the inputs for v in1 , v in2 , v in3 , v in4 respectively. assuming lk1 to lk4 are in place, these input signals are fed to four buffer amplifiers, ic1, before being applied to the ad7874. the use of an external clock source is optional; there is a shorting plug (lk5) on the ad7874 clk input which must be connected to either C5 v (for the adcs own internal clock) or to skt5. skt6 and skt7 provide the reference and convst inputs respectively. shorting plug lk6 provides the option of using the external ref- erence or the adcs own internal reference. db10 db8 db6 db4 db2 db0 gnd r/w rd cs 1 3 5 7 9 13 15 17 19 25 23 21 11 n/c n/c 2 4 6 8 10 14 16 18 20 26 24 22 12 db11 db9 db7 db5 db3 db1 gnd strb int n/c n/c n/c 5v + 5v + figure 19. skt8, idc connector pinout power supply connections the pcb requires two analog power supplies and one 5 v digi- tal supply. the analog supplies are labeled v+ and vC and the range for both supplies is 12 v to 15 v (see silkscreen in figure 23). connection to the 5 v digital supply is made via skt8. the +5 v supply and the C5 v supply required by the ad7874 are generated from voltage regulators (ic3 and ic4) on the v+ and vC supplies.
ad7874 rev. c C14C ic1 ad713 c4 c3 c1 c2 lk1 lk2 lk3 lk4 c7 c8 v dd c5 c6 v ss in out skt1 skt2 skt3 skt4 a b ab clk skt5 lk5 reference skt6 convst skt6 ic5 ic5 r1 r2 a b skt8 dgnd 11 22 8 5 23, 24 2 1 3 25, 26 data bus 5v + v ss clk ic2 ad7874 v dd convst db11 db0 int cs rd ref in dgnd agnd v in3 v in4 v in1 v in2 ic3 78l05 v + ic4 79l05 ref out v figure 20. data acquisition circuit using the ad7874 figure 21. pcb silkscreen for figure 20
ad7874 rev. c C15C figure 22. pcb component side layout for the circuit of figure 20 figure 23. pcb solder side layout for the circuit of figure 20
ad7874 rev. c C16C c1388aC5C5/91 shorting plug options there are seven shorting plug options which must be set before using the board. these are outlined below: lk1Clk4 connects the analog inputs to the buffer amplifi- ers. the analog inputs may also be connected to a component grid for signal conditioning. lk5 selects either the ad7874 internal clock or an ex- ternal clock source. lk6 selects either the ad7874 internal reference or an external reference source. lk7 connects the ad7874 rd input directly to the rd input of skt8 or to a decoded strb and r/ w input. this shorting plug setting depends on the microprocessor, e.g., the tms32020 and 68000 require a decoded rd signal. component list ic1 ad713 quad op amp ic2 ad7874 analog-to-digital converter ic3 mc78l05 +5 v regulator ic4 mc79l05 C5 v regulator ic5 74hc00 quad nand gate c1, c3, c5, c7, c9 10 m f capacitors c2, c4, c6, c8, c10 0.1 m f capacitors r1, r2 10 k w pull-up resistors lk1, lk2, lk3 shorting plugs lk4, lk5, lk6 lk7 skt1, skt2, skt3, bnc sockets skt4, skt5, skt6, skt7 skt8 26-contact (2-row) idc connector printed in u.s.a. outline dimensions dimensions shown in inches and (mm). plastic (n-28) cerdip (q-28) soic (r-28) lccc (e-28a) 0.458 (11.63) 2 0.442 (11.23) bottom view no. 1 pin index 0.055 (1.40) 0.045 (1.14) 0.028 (0.71) 0.022 (0.56) 0.050 0.005 (1.27 0.13) 0.040 x 45 (1.02 x 45 ) ref 3 plcs 0.020 x 45 (0.51 x 45 ) ref 0.100 (2.54) 1 0.064 (1.63) notes 1. this dimension controls the overall package thickness. 2. applies to all four sides. 3. all terminals are gold plated. 28 0.075 (1.91) ref

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